Heterogeneous back-end-of-line integration of thin-film lithium niobate on active silicon photonics for single-chip optical transceivers
Accelerating AI/ML & Cloud Infrastructure with Next-Gen Photonic Transceivers
Authored by Lingfeng Wu, Zhonghao Zhou, Weilong Ma, Haohua Wang, Ziliang Ruan, Changjian Guo, Shiqing Gao, Zhishan Huang, Lu Qi, Jie Liu, Jing Feng, Dapeng Liu, Kaixuan Chen, and Liu Liu.
Unlocking unprecedented bandwidth and energy efficiency through novel BEOL integration of TFLN and active Silicon Photonics.
Revolutionizing Optical Interconnects for Data-Intensive Computing
Traditional silicon modulators pose a significant bottleneck for high-speed optical transceivers due to inherent material limitations. This research introduces a groundbreaking heterogeneous integration approach, embedding high-performance thin-film lithium niobate (TFLN) modulators directly onto active silicon photonics chips. This fusion delivers superior bandwidth and integration density, critical for the demands of AI, cloud, and machine learning infrastructures.
>60 GHz
Electrical-to-Electrical Bandwidth
Unprecedented end-to-end link speed for high-capacity data flow.
100 GHz
TFLN Modulator Bandwidth
Peak performance achieved by integrated thin-film lithium niobate modulators.
128 GBaud
OOK Data Rate Achieved
Enabling advanced modulation schemes for energy-efficient data transmission.
0.11 dB
Ultra-Low Interlayer Coupling Loss
Efficient optical coupling between Si and TFLN waveguides for minimal signal degradation.
Deep Analysis & Enterprise Applications
Select a topic to dive deeper, then explore the specific findings from the research, rebuilt as interactive, enterprise-focused modules.
Integration Breakthrough: BEOL TFLN on Active Silicon Photonics
Problem: Silicon photonics offers density but its modulators are a key bottleneck, while direct integration of high-performance materials like TFLN with active silicon platforms faces severe process incompatibilities, limiting co-integration of critical components like photodetectors and complex metallization.
Solution: Our breakthrough lies in the first heterogeneous Back-End-of-Line (BEOL) integration of Thin-Film Lithium Niobate (TFLN) with a full-functional and active silicon photonics platform. This is achieved via trench-based die-to-wafer bonding, introducing TFLN after all CMOS-compatible processes for silicon photonics are completed. This strategy preserves the integrity of the active silicon devices while leveraging TFLN's superior electro-optic properties.
Outcome: This novel BEOL approach enables seamless co-integration of high-performance TFLN modulators, 56-GHz Ge photodetectors, Si/SiN passive components, and multilayer metallization on a single silicon chip. Crucially, it ensures efficient inter-layer and inter-material optical coupling through carefully engineered Vertical Adiabatic Couplers (VACs) within the trenches, overcoming previous integration barriers.
Performance Benchmarks: Unrivaled Speed and Efficiency
Problem: Achieving ultra-high bandwidth and low power consumption on a single chip, especially for modulator-photodetector links, has been a persistent challenge, with traditional silicon modulators often exhibiting trade-offs between speed and drive voltage.
Solution: We demonstrate a record ~100 GHz electro-optic bandwidth for the TFLN modulators with a competitive VπL of 2.8 V-cm. Our integrated Ge photodetectors show robust performance with 56 GHz bandwidth at -2V bias, maintaining integrity post-bonding. The full on-chip optical data links exhibit >60 GHz electrical-to-electrical bandwidth, limited primarily by the photodetector, showcasing the potential for extremely high-speed interconnects.
Outcome: The platform supports data transmissions at 128-GBaud OOK (BER < 2.4×10^-4) and 100-GBaud PAM4 (BER < 3.8×10^-3), both below forward error correction thresholds. This confirms the practical viability of the integrated solution for next-generation data rates required by AI/ML and cloud computing infrastructure.
Scalability & Future-Proofing: A Path to Wafer-Scale Computing
Problem: Developing a photonic integration platform that is both high-performance and compatible with existing large-scale manufacturing processes, while also supporting future complex functionalities, remains a significant hurdle for widespread adoption.
Solution: By adopting a BEOL integration strategy, our platform retains full CMOS compatibility with standard silicon photonics PDKs, ensuring scalable manufacturing and cost-effectiveness. The TFLN integration step, including patterning and top-most metallization, can be performed in a separate fab with moderate critical dimension requirements, decentralizing complex processing. Furthermore, the platform's compatibility with SiN layers enables tri-layer integration, opening doors for even more complex functionalities.
Outcome: This establishes a scalable and energy-efficient foundation for single-chip optical transceivers for data-center interconnects, microwave photonics, and dense on-chip data links towards future optical network-on-chips (NoCs) in wafer-scale computing. Future improvements, such as capacitively loaded traveling-wave electrodes and differential drive, promise even higher modulation efficiency and bandwidth, pushing towards submillimeter modulator footprints and terabit-per-second transmission capabilities.
100 GHz
Peak TFLN Modulator Bandwidth
The integrated thin-film lithium niobate modulators achieve an impressive 100 GHz electro-optic bandwidth, setting a new benchmark for high-speed optical signal generation on a silicon platform.
Enterprise Process Flow
Full Silicon Photonics Fabrication (Si waveguides, Ge, SiN, Heaters, Multilayer Metals)
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Trench Opening for Modulation Regions
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Die-to-Wafer Bonding of LNOI using BCB
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LNOI Substrate/Oxide Removal & TFLN Waveguide Definition
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Final TFLN Metallization and Pad Opening
| Feature | Conventional TFLN-Si/SiN Integration (Passive) | BEOL TFLN-Active Si Integration (This Work) |
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| Active Si Photonics Compatibility |
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| Modulator Bandwidth Potential |
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| Photodetector Integration |
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| Manufacturing Compatibility |
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| Optical Link Bandwidth |
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Impact on Data Center Interconnects
The explosive demand from Artificial Intelligence, Cloud Computing, and Large-Scale Machine Learning drives an urgent need for high-bandwidth, low-power, and highly integrated optical interconnects. Our heterogeneous BEOL integration platform directly addresses this by enabling single-chip optical transceivers that combine the superior modulation capabilities of TFLN with the robust detection of active silicon photonics. This allows for 128-GBaud OOK and 100-GBaud PAM4 transmission below FEC thresholds, setting a new standard for energy-efficient, high-capacity data links within data centers. The platform's CMOS compatibility and potential for tri-layer SiN integration ensure it is not only performant but also scalable and future-proof for the evolving demands of wafer-scale computing and Optical Network-on-Chips (NoCs).
Calculate Your Potential ROI with Advanced Photonics
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Your Enterprise Photonics Roadmap
Implementing this cutting-edge integration requires a structured approach. Here’s a high-level roadmap inspired by the research, detailing the typical phases of adopting advanced photonic solutions.
Phase 1: Feasibility Assessment & Design Adaptation
Evaluate current infrastructure, identify key data bottlenecks, and adapt BEOL integration designs to specific enterprise requirements. This involves leveraging CMOS-compatible PDKs and ensuring efficient inter-layer coupling strategies for your unique system architecture.
Phase 2: Prototype Development & Performance Verification
Fabricate initial prototypes using the trench-based die-to-wafer bonding of TFLN onto your active silicon photonics platform. Rigorously test modulator bandwidth, photodetector efficiency, and full optical link performance (e.g., electrical-to-electrical bandwidth, BER) to validate the integration process.
Phase 3: Scaled Manufacturing & System Integration
Transition from prototyping to scalable manufacturing processes, utilizing separate fabs for TFLN patterning if needed. Integrate the single-chip optical transceivers into larger system architectures, such as data center interconnects or optical Network-on-Chips (NoCs), focusing on power efficiency and density.
Phase 4: Optimization & Future-Proofing
Continuously optimize performance, exploring advancements like capacitively loaded traveling-wave electrodes, differential drives, or tri-layer SiN integration. Plan for future enhancements to meet evolving demands of AI/ML and quantum computing, ensuring your infrastructure remains at the forefront of photonic technology.
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