Enterprise AI Analysis
AHASD: Asynchronous Heterogeneous Architecture for LLM Adaptive Drafting Speculative Decoding on Mobile Devices
AHASD introduces an asynchronous heterogeneous architecture for LLM speculative decoding on mobile NPU-PIM systems. It decouples drafting and verification tasks, incorporates dynamic controls for adaptive drafting, and uses in-memory computing to improve efficiency. This results in significant throughput and energy efficiency gains over GPU-only and state-of-the-art GPU+PIM baselines.
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Throughput Improvement
Energy Efficiency Gain
Hardware Overhead
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Asynchronous Heterogeneous Architecture
AHASD proposes a novel task-level asynchronous architecture for mobile NPU-PIM systems, decoupling DLM and TLM operations to maximize parallel execution and minimize idle overhead.
4.2x
Throughput improvement over GPU-only baseline.
Enterprise Process Flow
DLM Drafting on PIM
→
Unverified Draft Queue
→
NPU Verification
→
Feedback Queue
→
TLM Accepted Tokens
| Feature | SpecPIM | AHASD |
|---|---|---|
| Execution Model | Operator-level synchronous | Task-level asynchronous |
| Draft Length Handling | Fixed assumption | Adaptive, dynamic |
| PIM Utilization | Fluctuates with draft length | Optimized with pre-verification |
| Synchronization Overhead | High due to operator sync | Reduced due to task decoupling |
| Pre-Verification | Limited/none | Time-Aware small-batch pre-verification |
Adaptive Drafting & Pre-Verification Controls
AHASD integrates Entropy-History-Aware Drafting Control and Time-Aware Pre-Verification Control for dynamic management of adaptive drafting, suppressing low-confidence drafts and optimizing pre-verification timing.
5.6x
Energy efficiency gain over GPU-only baseline.
Impact of Adaptive Controls
Empirical data shows that dynamic control mechanisms in AHASD, such as Entropy-History-Aware Drafting Control, significantly reduce computational waste from low-acceptance drafts. This leads to a 24.6% recovery in acceptance rate and a 3.4x throughput increase compared to just asynchronous NPU+PIM with AAU. Furthermore, Time-Aware Pre-Verification Control ensures optimal PIM utilization by inserting small-batch verifications without causing NPU idling.
LPDDR5-PIM Integration
AHASD enhances LPDDR5-PIM with an Attention Algorithm Unit (AAU) and Gated Task Scheduling Unit, enabling attention link localization and sub-microsecond task switching, reducing cross-chip communication overhead.
<3%
Hardware overhead of DRAM area.
AAU & Gated Task Scheduling
The Attention Algorithm Unit (AAU) within LPDDR5-PIM executes nonlinear operators and reduction operations directly in the memory path, eliminating data transfer to the NPU. This contributes to a throughput increase of 2.7x. The Gated Task Scheduling Unit enables sub-microsecond task switching and efficient pre-verification execution on PIM, addressing operator-level synchronization inefficiencies.
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