Neuromorphic Computing
Investigating non-volatile memory architectures for neuromorphic systems with CMOS spike-timed synaptic plasticity
This research introduces novel neuromorphic circuits, adjustable synapse circuits, and a CMOS Spike-Based Driven Synaptic Plasticity (CSBDSP) learning algorithm to create compressed and physiologically realistic Spiking Convolutional Neural Networks (SCNNs) with low power dissipation. It focuses on implementing a novel OxRAM-based Non-Volatile CMOS SRAM (NVSRAM) device, specifically a 9T-SRAM architecture integrated with Oxide Resistive RAM (Ox-RAM). This design significantly enhances stability, minimizes leakage current, and optimizes read/write performance compared to conventional 6T SRAMs. The study also explores DG FINFET (Double Gate Fin Shaped Field Effect Transistor) approaches to further reduce SRAM cell power consumption, concluding that DG FINFET-based SRAM cells offer superior power dissipation. The circuits are fabricated at 180 nm and 90 nm using high voltage CMOS technology, highlighting improvements in design impenetrability, leakage current, and power consumption.
Executive Impact: Key Metrics & Business Value
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Improved Stability (%)
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Reduced Leakage Current (Avg %)
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Enhanced Read/Write Performance (Avg %)
0 nW
Power Consumption (nW) (9TNVRAM, 90nm)
Deep Analysis & Enterprise Applications
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Explores the 9T-SRAM architecture integrated with OxRAM technology, detailing its design advantages over conventional 6T SRAM in terms of stability, leakage current, and performance. This section highlights how the non-volatile nature of OxRAM is leveraged for data retention during power-off.
Examines the application of Double Gate Fin Shaped Field Effect Transistor (DG FINFET) techniques to SRAM cells. This method significantly reduces power consumption and improves gate control, contributing to enhanced energy efficiency for neuromorphic applications.
Delves into the CMOS Spike Based Driven Synaptic Plasticity (CSBDSP) learning algorithm. This biologically inspired learning rule enables efficient and adaptable learning in neuromorphic systems, crucial for the brain's ability to adapt to changing conditions.
2.52 nJ
Energy per Spike for Synapse SDSP at 50Hz
NVSRAM Data Flow with OxRAM Integration
SRAM data generated
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Power-off detected
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Data stored in OxCRAM
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Power restored
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Data transferred to SRAM
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SRAM volatility rectified
| Feature | 9T SRAM | NVSRAM (OxRAM) with DG FINFET |
|---|---|---|
| Power Consumption | 10.5 nW | 7.4 nW |
| Leakage Current | 7.4 nA | 3.2 nA |
| Delay | 34.5 ns | 21 ns |
| Volatility | Volatile | Non-Volatile |
Enhanced Neuromorphic System Design
The integration of OxRAM-based NVSRAM and DG FINFET techniques enables the creation of highly efficient neuromorphic systems. This approach addresses critical challenges in scalability and energy consumption, paving the way for more powerful and compact AI hardware.
Impact:
Achieved significant improvements in power efficiency (3.5 nW for 9TNVRAM at 90nm) and reduced leakage current, making these architectures ideal for low-power edge AI applications. The non-volatile nature ensures data integrity during power cycling, critical for always-on devices.
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Estimated Annual Savings
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Your AI Implementation Roadmap
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Phase 1: Architecture Blueprint & Simulation
Develop detailed architectural blueprints for the NVSRAM and CSBDSP circuits. Conduct comprehensive simulations at 180nm and 90nm CMOS technologies to validate performance, power, and stability against baseline SRAM designs.
Phase 2: Prototype Fabrication & Characterization
Fabricate test chips incorporating the proposed OxRAM-based 9T NVSRAM and DG FINFET SRAM cells. Perform physical characterization to measure actual leakage currents, power dissipation, and read/write speeds, comparing them with simulation results.
Phase 3: Neuromorphic System Integration & Testing
Integrate the optimized NVSRAM cells into a small-scale neuromorphic system (SCNN). Implement and test the CSBDSP learning algorithm, evaluating its efficiency, adaptability, and overall performance in tasks like pattern recognition or data processing.
Phase 4: Scalability Assessment & Optimization
Assess the scalability of the architecture for larger neuromorphic systems. Identify bottlenecks and further optimize the design for high density and ultra-low power consumption, preparing for potential commercial applications in edge computing and AI.
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